As a data processing apparatus related to the present invention, there is a processor called a SVP (Serial Video Processor) described in Section 3.1 on Page 17 of the IEEE 1990 CUSTOM INTEGRATED CIRCUITS CONFERENCE. Composed of 1,024 processors integrated in a single chip, the SVP is a processor for carrying out real time digital processing on a video signal. The SVP has a SIMD (Single Instruction stream/Multiple Data stream) structure which allows pixel data on a horizontal scanning line to be processed concurrently. SIMD is the name of one of data processing methods adopted by a computer whereby data of different kinds is processed concurrently as if the data pertained to 1 job.
FIG. 1 is a block diagram showing a typical configuration of a conventional SIMD control parallel processor. As shown in the figure, the SIMD control parallel processor comprises a program control apparatus 1, an input SAM (Serial Access Memory) unit 3, a data memory unit 4, a processing circuit unit 5 and an output SAM unit 6.
The input SAM unit 3, the data memory unit 4, the processing circuit unit 5 and the output SAM unit 6 constitute a group of parallel element processors 2 arranged in a linear array. The element processors 2 are interlocked with each other under control in accordance with a program of the program control apparatus 1. The program control apparatus 1 comprises a program memory for storing the program in advance and a sequence control circuit for carrying on the program. The program control apparatus 1 generates a variety of control signals in accordance with the program in order to control a variety of circuits.
It should be noted that the input SAM (Serial Access Memory) unit 3, the data memory unit 4, and the output SAM unit 6 are each implemented as a memory, detailed explanation of which is omitted. In an apparatus shown in FIG. 3, row address decoders for these memories are included in the program control apparatus 1.
One element processor 2 is represented by a hatched block in FIG. 1. A plurality of element processors 2 are arranged in parallel, that is, in the horizontal direction of the figure. That is to say, the element processor 2 indicated by the hatch block comprises components of 1 processor.
Next, the operation of the linear array parallel processor for carrying out video processing shown in FIG. 1 is explained.
Input data, strictly speaking, picture data of 1 pixel, is supplied to the input SAM unit 3 in accordance with a control signal output by the program control apparatus 1. The element processors 2 from the leftmost one to the rightmost one shown in the figure sequentially process the data. That is to say, pieces of input data are supplied sequentially to input SAM cells of the input SAM unit 3 from the leftmost one to the rightmost one shown in the figure.
Since the number of element processors 2 is at least equal to the pixel count H in one horizontal scanning period of a video signal, pixel data of one horizontal scanning period of a video signal can be accumulated in the input SAM unit 3. The operation to supply input data is repeated for each horizontal scanning period.
Each time data of 1 horizontal scanning period of a picture signal is accumulated in the input SAM unit 3 as described above, the program control apparatus 1 carries out processing by executing SIMD control on the input SAM unit 3, the data memory unit 4, the processing circuit unit 5 and the output SAM unit 6 in accordance with the program as described below. In addition, the SIMD control causes the following operations to be executed in all the element processors 2 concurrently in the same way.
The input data of 1 horizontal scanning period of a picture signal accumulated in the input SAM unit 3 is, if necessary, transferred from the input SAM unit 3 to the data memory unit 4 during the next horizontal scanning period to be used in the subsequent processing.
In a transfer of data from the input SAM unit 3 to the data memory unit 4, the program control apparatus 1 makes an access to data of a predetermined bit count in the input SAM unit 3 selected by an input SAM read signal, and then outputs a memory access signal to write the data into a predetermined memory cell of the data memory unit 4.
Next, the program control apparatus 1 supplies data stored in the data memory unit 4 of each element processor 2 to the processing circuit unit 5 of the element processor 2 in accordance with the program and lets the processing circuit unit 5 carry out arithmetic and logic processing on the data supplied thereto. Results of processing are then written at a predetermined address of the data memory unit 4.
FIG. 2 is a block diagram showing a typical configuration of the processing circuit unit 5. Pieces of data from the data memory unit 4 are supplied to a register 24 by way of a selector 20, a register 25 by way of a selector 21 and a register 26 by way of a selector 22. The selector 20 selects the value 1 set in advance, the piece of data output by the data memory unit 4 or data stored in the register 24 and outputs the selected one to the register 24. A selector 21 selects the value 1 set in advance, the value 0 also set in advance or the piece of data output by the data memory unit 4 and outputs the selected one to a register 25. By the same token, a selector 22 selects the value 1 set in advance, the value 0 also set in advance or the piece of data output by the data memory unit 4 and outputs the selected one to a register 26. Signals generated by the program control apparatus 1 control how the selectors 20, 21 and 22 select one of their 3 inputs. A register 27 is used for storing data representing a carry-over generated by a full adder 31.
A logical product circuit 28 computes a logical product of the data stored in the register 24 and data stored in the register 25. An exclusive logical sum circuit 29 computes an exclusive logical sum of data output by the logical product circuit 28 and data supplied by the program control apparatus 1 and supplies the exclusive logical sum to the full adder 31. The full adder 31 also receives data stored in the register 26 and data stored in the register 27. The full adder 31 computes the sum of these 3 inputs, outputting the sum and its carry-over to a selector 32. The carry-over is also supplied to the register 27 by way of the selector 23.
A selector 30 selects either the data output by the register 25 or data output by the register 26 and outputs the selected one to the selector 32. The selector 32 selects 1 of 3 inputs: the data output by the selector 30, the sum output by the full adder 31 and the carry-over also output by the full adder 31 and outputs the selected one to the data memory unit 4. Signals generated by the program control apparatus 1 control how the selectors 30 and 32 select one of their inputs.
Assume that, for example, a signal generated by the program control apparatus 1 controls the selector 20 to let the selector 20 select the value 1 to be stored in the register 24. In this case, since the logic value 1 is stored in the register 24, data stored in the register 25 from the data memory unit 4 passes through the logical product circuit 28 as it is, entering the full adder 31 by way of the exclusive sum circuit 29. The full adder 31 computes the sum of the data supplied from the register 25 by way of the exclusive logical circuit 29, data stored in the register 26 from the data memory unit 4 and data representing a carry-over generated in previous processing and stored in the register 27. The sum and a newly generated carry-over are output to the selector 32. As described above, the carry-over is also supplied to the selector 27 by way of the selector 23 to be stored therein.
The program control apparatus 1 is also capable of controlling the selector 32 to select the carry-over generated by the full adder 31 to be output to the data memory unit 4. In addition, the program control apparatus 1 is also capable of controlling the selector 30 to select either the data output by the register 25 or data output by the register 26 to be output to data memory unit 4 by way of the selector 32 which is also controlled thereby to select the data selected by the selector 30.
When it is desired to supply data output by the logical product circuit 28 to the full adder 31 by logically inverting the data, the program control apparatus 1 outputs the logic value 1 to the exclusive sum circuit 29 as one of the inputs thereof. With the logic value 1 supplied to the exclusive sum circuit 29 as one of the inputs thereof, the exclusive sum circuit 29 will pass on a logic value 1 received from the logical product circuit 28 as a logic value 0 and pass on a logic value 0 received from the logical product circuit 28 as a logic value 1.
When it is desired to compute a logical product of newly input data and immediately previous data, the program control apparatus 1 controls the selector 20 to again select data stored in the register 24. With the selector 20 again selecting the data stored in the register 24, the logical product circuit 28 receives the current data and the immediately previous data and computes their logical product because the current data is stored in the register 25. By controlling the selector 20 to select the output of the register 24 repeatedly, processing can be carried out on new input data and previous input data.
When processing allocated to a 1 horizontal scanning period as described above is finished, data processed in the 1 horizontal scanning period is transferred to the output SAM unit 6 by the end of the 1 horizontal scanning period.
As described above, transfers of input data stored in the input SAM unit 3 to the data memory unit 4, processing of the data carried out by the processing circuit unit 5 and transfers of processing results to the output SAM unit 6 during the 1 horizontal scanning period are executed in accordance with the SIMD control program in bit units. These pieces of processing are carried out repeatedly in horizontal scanning period units.
The data transferred to the output SAM unit 6 is further output from the output SAM unit 6 in the next horizontal scanning period.
As described above, 3 pieces of processing are carried out on each piece of input data. The 3 pieces of processing are the input processing to write input data into the input SAM unit 3, the arithmetic/logic processing controlled by the program control apparatus 1 and the output processing to output results of processing from the output SAM unit 6. The arithmetic/logic processing controlled by the program control apparatus 1 comprises transfers of input data stored in the input SAM unit 3 to the data memory unit 4, processing of the data carried out by the processing circuit unit 5 and transfers of processing results to the output SAM unit 6. It should be noted that the 3 pieces of processing are executed as pipeline processing with 1 horizontal scanning period of the picture signal taken as a unit.
Pay attention to data input in 1 horizontal scanning period. Typically, it takes as much time as about 1 horizontal scanning period to complete each of the 3 pieces of processing. Thus, in order to complete the 3 pieces of processing for the data, it takes as much time as about 3 horizontal scanning periods. Since the 3 pieces of processing are pipeline processing which is carried out concurrently, that is, processing wherein the second piece of processing for data of a horizontal scanning period is carried out concurrently with the first piece of processing for data of the following horizontal scanning period, however, it takes as much time as only about 1 horizontal scanning period to complete the 3 pieces of processing for data of 1 horizontal scanning period on the average.
With the conventional signal processing apparatus described above, however, timing to read out data from the input SAM unit may be different from timing to write results of processing into the output SAM unit in processing such as conversion of the number of lines. Of course, this timing discrepancy problem can be solved, for example, by providing a frame memory at a stage prior to the signal processing apparatus. However, such a frame memory will raise another problem of a rising cost.
In order to solve the timing discrepancy problem described above, it is necessary to suspend the processing when a request to read out data from the input SAM unit and a request to write results of processing into the output SAM unit are issued.
It is thus an object of the present invention addressing the problems described above to provide a data processing apparatus which can be made at a low cost and is capable of temporarily storing data read out from the input SAM unit into a memory in case processing of data of a previous line has not been completed yet and capable of reading out pieces of data from the memory sequentially for processing on a FIFO basis, that is, in an order the pieces of data were written into the memory.
A data processing apparatus provided by the invention comprises:
an address modifying means for modifying an address specified by a program in an access to a data storage unit; and
an information generating means for generating control information for controlling modification of an address carried out by said address modifying means in accordance with an instruction issued by said program.
A data processing method adopted in said data processing apparatus comprises:
an address modifying step of modifying an address specified by said program in an access to said data storage unit; and
an information generating step of generating control information for controlling modification of an address carried out at said address modifying step in accordance with an instruction issued by said program.
In said data processing apparatus,
said address modifying means modifies an address specified by said program in an access to said data storage unit; and
said information generating means generates control information for controlling modification of an address carried out by said address modifying means in accordance with an instruction issued by said program.
According to said data processing method adopted in said data processing apparatus,
at said address modifying step, an address specified by said program in an access to said data storage unit is modified; and
at said information generating step, control information for controlling modification of an address carried out at said address modifying step is generated in accordance with an instruction issued by said program.
Preferred embodiments of the present invention will be described below. In order to clarify relations associating means described in claims of the present specification with elements employed in the embodiments, characteristics of the present invention are explained below by adding a typical element of an embodiment enclosed in parentheses after a means in a claim which corresponds to the element in the form xe2x80x9ca means (implemented for example by a typical element)xe2x80x9d. It is needless to say, however, that the description is not intended to be construed in a limiting sense. That is to say, the implementation of the means is not limited to the typical element corresponding to the means.
A data processing apparatus provided by the present invention comprises:
a data storage unit (implemented for example by a data memory unit 4 shown in FIG. 1) for storing input data;
a data processing unit (implemented for example a processing circuit unit 5 shown in FIG. 1) for processing data stored in said data storage unit;
a control unit (implemented for example by a program control apparatus 1 shown in FIG. 1) for controlling operations of said data storage unit and said data processing unit in accordance with a program;
an address modifying means (implemented for example by a memory write address modifying circuit 55 employed in said program control apparatus 1 shown in FIG. 3) for modifying an address specified by said program in an access to said data storage unit; and
an information generating means (implemented for example by a write port address modification information generating unit 52 employed in said program control apparatus 1 shown in FIG. 3) for generating control information for controlling modification of an address carried out by said address modifying means in accordance with an instruction issued by said program.
Said information generating means of said data processing apparatus is further provided with a flag setting/resetting means (implemented for example by a flag setting/resetting means 54 employed in said program control apparatus 1 shown in FIG. 3) for setting/resetting a flag on the basis of an addition value held in a second information holding means, the number of times an operation to modify a memory address has been carried out held in a fourth information holding means and the maximum number of times an operation to modify a memory address can be carried out held in a fifth information holding means and said program controls said information generating means in accordance with said flag.
As described above, according to the data processing apparatus claimed as claim 1, a memory address issued by a program is modified in accordance with control information generated in dependence on an instruction from the program specifying the memory address, making it possible to prevent the description of the program from becoming complicated.